The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
A dual damascene process has been developed to form the increasingly interconnect features such as vias and metal lines. The dual damascene process involves forming gaps or openings. Traditional dual damascene processes use a seed layer plus a copper plating process to fill the gaps. However, this approach may run into problems as semiconductor device sizes continue to shrink. For example, in a 20-nanometer (nm) fabrication process, the gaps may become too narrow and thus may not be properly filled by conventional dual damascene processes. The top portion of the gap may be blocked, which may create a void underneath. Consequently, semiconductor device performance is degraded.
Therefore, while existing dual damascene processes have been generally adequate for their intended purposes, they are not entirely satisfactory in every aspect.